Method and structure for ultra-low contact resistance CMOS...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S683000

Reexamination Certificate

active

06972250

ABSTRACT:
A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.

REFERENCES:
patent: 5818100 (1998-10-01), Grider et al.
patent: 5955745 (1999-09-01), Yamazaki
patent: 6214679 (2001-04-01), Murthy et al.
patent: 6235568 (2001-05-01), Murthy et al.

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