Method and structure for forming high-k gates

Details Method and structure for forming high-k gates Method and structure for forming high-k gates

2006-07-04

2006-07-04

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

07071066

ABSTRACT:
A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

REFERENCES:
patent: 5425392 (1995-06-01), Thakur et al.
patent: 6020260 (2000-02-01), Gardner
patent: 6573193 (2003-06-01), Yu et al.
patent: 6603181 (2003-08-01), Solomon et al.
patent: 6682973 (2004-01-01), Paton et al.
patent: 6717226 (2004-04-01), Hegde et al.

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