Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-02-27
2000-06-06
Tu, Christine
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
G01R 3128
Patent
active
06073258&
ABSTRACT:
A method and device for performing two dimensional redundancy determinations on embedded memories is provided. The method and device permit the calculation and implementation of two-dimensional redundancy without saving a failure map of the memory being tested. The method and device dynamically determines whether any failed memory cells are present within the array and attempts to repair the cells. Two logic procedures are implemented: a "must fix" word and bit line procedure and a "single cell" repair procedure. The "must fix" word and bit line procedure counts the number of failed first dimensional memory components (i.e., bit lines or word lines) along a second dimensional memory component (i.e., word line or bit line). If the number of failed memory elements is greater than the number of redundant first dimensional components, a redundant second dimensional component is soft-fused in placed of the second dimensional memory component. The "single cell" repair procedure attempts to repair any failed single memory cells by soft-fusing redundant word or bit lines for the failed single memory cell's word or bit line, as appropriate.
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Hogg William N.
International Business Machines - Corporation
Tu Christine
LandOfFree
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