Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-10-03
2006-10-03
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000, C714S742000
Reexamination Certificate
active
07117403
ABSTRACT:
The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.
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Ernst Wolfgang
Krause Gunnar
Kuhn Justus
Lüpke Jens
Müller Jochen
Greenberg Laurence A.
Infineon - Technologies AG
Lamarre Guy
Locher Ralph E.
Stemer Werner H.
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