Method and configuration for the output of bit error tables...

Details Method and configuration for the output of bit error tables... Method and configuration for the output of bit error tables...

2005-06-21

2005-06-21

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000

Reexamination Certificate

active

06910163

ABSTRACT:
A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the memory device following a request from the test apparatus. Then, the bit error tables are transmitted sequentially to the test apparatus for further processing.

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patent: 101 20 255 (2002-11-01), None

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