Method and circuit for controlling a precharge cycle of a memory

Details Method and circuit for controlling a precharge cycle of a memory Method and circuit for controlling a precharge cycle of a memory

1997-10-27

1998-10-27

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Precharge

365233, G11C 700

Patent

active

058286128

ABSTRACT:
A method and circuit for optimally controlling memory array bit line precharge timing to increase memory frequency of operation by generating a precharge output (110) for memory array bit lines in response to the earliest asserted control input among precharge control inputs. A write precharge signal (218) early enables a write precharge operation by enabling the precharge signal (110) a delayed period after an enabling falling dock edge of clock (104), as indicated by a write precharge enable signal (210), and during a write cycle, as indicated by a write precharge trigger (212). Thereafter, a default precharge trigger (216) is enabled to ensure that write precharging operation continues for an extended and optimal duration. A read precharge trigger (214) enables precharging after a read operation by enabling the precharge signal (110) in close proximity to the disabling of read sense amplifiers within the memory array to enhance post-read precharging. Thereafter, the default precharge trigger (216), is enabled to ensure that the read precharging operation continues for an extended and optimal duration.

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