Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-12-12
2003-01-14
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06507924
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor memories, and more specifically to a method and circuit for testing memory cells in a synchronous static random access memory by modulating the rate of change of voltages developed on digit lines when writing data to the memory cells.
BACKGROUND OF THE INVENTION
During the manufacture of static random access memories (“SRAMs”), as well as other types of semiconductor memories, it is necessary to test the SRAM to ensure it is operating properly. An SRAM normally includes an array of memory cells arranged in rows and columns. The memory cells are tested by writing data to and reading data from the individual memory cells. Numerous test methodologies are utilized in testing for various types of defects that can occur in SRAM memory cells, such as shorted digit lines or inoperable access transistors. For example, a binary “1” or binary “0” may be written to and read from each SRAM memory cell, or alternating patterns of binary 1's and 0's may be written to and read from the memory cells in each row.
FIG. 1
illustrates a conventional SRAM memory cell
10
coupled between a pair of complementary digit lines DL and {overscore (DL)}. The SRAM memory cell
10
includes a conventional pair of cross-coupled inverters
12
and
14
comprising the transistors
16
,
18
and
20
,
22
, respectively, coupled between a supply voltage source V
CC
and ground. As known in the art, each of the inverters
12
and
14
has an associated threshold voltage V
T
corresponding to the voltage a signal on its input must reach before the inverter begins driving its output to the complement of the input signal. A pair of access transistors
24
and
26
couple an output node
17
of the inverter
12
to the digit line {overscore (DL)} and an output node
21
of the inverter
14
to the digit line DL, respectively, in response to a word line signal WL. A write driver circuit
28
receives complementary data signals D and {overscore (D)} and develops voltages on the digit lines DL and {overscore (DL)} corresponding to the complementary data signals D and {overscore (D)}, respectively.
The operation of the SRAM memory cell
10
during a typical write operation will now be described with reference to the signal timing diagram of FIG.
2
. At the time t
0
, the data signals D and {overscore (D)} go high and low, respectively, corresponding to the data to be stored in the memory cell
10
. In response to the data signals D and {overscore (D)}, the write driver circuit
28
drives the voltages on the digit lines DL and {overscore (DL)} high and low, respectively. The write driver circuit
28
cannot instantaneously drive the voltages on the digit lines DL and {overscore (DL)} to their desired levels, however, because the digit lines DL and {overscore (DL)} are highly capacitive. The capacitances of the digit lines DL and {overscore (DL)} cause the voltages on the digit lines to gradually approach their desired levels. The word line WL is activated just after the time t
0
thereby coupling the nodes
17
and
21
to the digit lines {overscore (DL)} and DL, respectively. At a time t
1
, the voltages on the digit lines DL and {overscore (DL)} reach the threshold voltages V
T
of the inverters
12
and
14
, and the inverters begin driving the voltages on nodes
17
and
21
low and high, respectively. In other words, the inverter
12
begins driving the voltage on node
17
low in response to the high on the digit line DL. The voltage on node
17
is also driven low by the low going voltage on the digit line {overscore (DL)}. The inverter
14
operates in the same way to drive the voltage on node
21
high. In this way, the SRAM memory cell
10
drives the nodes
17
and
21
low and high, respectively, corresponding to the voltages developed on the digit lines {overscore (DL)} and DL. At a time t
2
, the word line WL is deactivated turning OFF the access transistors
24
and
26
and isolating the nodes
17
and
21
from the digit lines {overscore (DL)} and DL, respectively. The memory cell
10
maintains the voltages on the nodes
17
and
21
low and high, respectively, after the word line WL is deactivated and in this way stores the data written to the memory cell.
The threshold voltages V
T
of the inverters
12
and
14
determine when the inverters
12
and
14
begin turning ON and thereby determine when the memory cell
10
begins latching the data placed on the digit lines DL and {overscore (DL)}. The voltages on the digit lines DL and {overscore (DL)} must exceed the threshold voltages V
T
of the inverters
12
and
14
before the time t
2
, which is when the data signals D and {overscore (D)} change state and when the access transistors
24
and
26
are deactivated. The interval between the times t
0
and t
2
is the write pulse width t
WPW
of the data signals on the digit lines DL and {overscore (DL)}.
During the testing of SRAMs, it is desirable to perform margin tests on the SRAM memory cells in which the margins of the data signals developed on digit lines DL and {overscore (DL)} are varied. In a timing margin test, the write pulse width t
WPW
is made shorter than its normal duration. When the write pulse width twpw is shortened, the data signals on the digit lines DL and {overscore (DL)} may not exceed the threshold voltages V
T
of the inverters
12
and
14
during the write pulse width and the memory cell
10
may not latch the data placed on the digit lines DL and {overscore (DL)}. During normal operation of an SRAM slight variations in write pulse width t
WPW
may occur, and this type of margin test detects cells that may fail due to such slight variations. In asynchronous SRAMs, the duration of the write pulse width t
WPW
is controlled by external asynchronous control signals applied to the SRAM. Thus, the write pulse width t
WPW
can be easily adjusted by varying such external control signals. The write pulse width t
WPW
is shortened when writing data to the memory cells and then the data read from the memory cells to determine whether the memory cells properly stored the written data. In synchronous SRAMs, however, as well as other types of SRAMs, the write pulse width t
WPW
is constant and determined by a fixed internal signal that is not externally adjustable. Thus, in synchronous SRAMs, the write pulse width cannot be easily shortened to perform margin tests on the memory cells.
There is a need for performing margin tests of memory cells in synchronous SRAMs.
SUMMARY OF THE INVENTION
A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first drive node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second drive node. The test circuit develops a first impedance between the second drive node and a second voltage source when the test mode signal is active, and develops a second impedance between the second drive node and the second voltage source when the test mode signal is inactive.
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Lamarre Guy
Ton David
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