Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-04-20
2001-06-12
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000, C365S200000, C365S201000, C365S230030
Reexamination Certificate
active
06247153
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method and apparatus for testing a semiconductor memory device having a plurality of memory banks, by which the physical address of a defective memory cell can be found easily.
2. Description of the Related Art
Recently, a combined semiconductor memory device, i.e., a memory merged with a logic circuit (MML), has developed rapidly.
In highly integrated memories, redundant line analysis is performed, by which a high yield can be expected.
Here, since data input/output pins in a memory included in the MML are formed in plural formats, for example, ×64 , ×128, ×256, ×512, ×1024, and so on, the memory operates fast. At this time, due to the limit in the number of input/output pins of a memory testing apparatus, the multiple input/output memory cannot be tested. Also, due to the limit in generation of patterns by an algorithmic pattern generator, a logic circuit testing apparatus cannot test a highly integrated memory.
Thus, currently, the memory is directly accessed in a mode register setting method so that a plurality of data input/output lines are allocated to representative data output pins to test the memory in ×4, ×8, ×16, and so on.
For example, a 16-MB DRAM having 64 data input/output lines multiplexes the data input/output lines at a ratio of 8 to 1 in the mode register setting method during a direct access test mode, so that data is input from and output to 8 data pins.
A conventional DRAM testing apparatus comprises an error catching portion, a pattern generator, a comparator, and a data detector. The memory cells are tested by writing data to the memory cells according to an address pattern and data pattern generated by the pattern generator, and reading the data.
Thus, in a semiconductor memory device having a plurality of memory banks such as MML or synchronous DRAM, the separate memory banks are not differentiated. Thus, in the case of testing the memory cells using the DRAM testing apparatus, it is not possible to find which memory bank includes a defective memory cell. Also, since data is output to only a representative data pin among various data pins, by the MRS mode setting method, it is not possible to know through which data input/output line the data is output.
FIG. 1
shows the memory structure of a semiconductor memory device having a plurality of memory banks.
Referring to
FIG. 1
, the semiconductor memory device includes memory banks Bank
1
and Bank
2
each having 8 memory blocks Blocks
0
through
7
and Blocks
8
through
15
.
The memory blocks Blocks
0
through
15
each include two memory cell arrays. Each of the memory cell arrays includes memory cells allocated to 9-bit row addresses X
0
through X
255
or X
256
or X
511
, 8-bit column addresses Y
0
through Y
255
, and physical addresses composed of the row and column addresses, two row redundancy lines RR and four column redundancy lines for repairing a defective memory cell if any.
FIG. 2
is a schematic diagram illustrating how the semiconductor memory device shown in
FIG. 1
is tested.
Referring to
FIG. 2
, a conventional memory testing apparatus
12
includes an error catching portion
22
, e.g., an error catch RAM. The error catching portion
22
stores test results for the memory blocks of a semiconductor memory device
11
.
In more detail, the error catching portion
22
is divided into four addresses, and each address stores either the physical address of a defective memory cell of a memory portion
21
or the number of a data pin through which the data is output from the memory cell for the physical address, i.e., one of data pins DQ
0
through DQ
3
.
For example, the physical addresses of defective memory cells of the memory blocks Block
0
, Block
2
, Block
8
and Block
10
in which the eighth bit of the row address bit
8
, i.e., RA
8
, is logic low (“0”) and the data is output through a data in DQ
0
or DQ
3
, and the numbers of the data pins, are stored in the first address of the error catching portion
22
. Also, the physical addresses of defective memory cells of the memory blocks Block
5
, Block
7
, Block
13
and Block
15
in which the eighth bit of the row address, i.e., RA
8
, is logic high (“1”) and the data is output through a data pin DQ
1
or DQ
2
, and the numbers of the data pins, are stored in the fourth address of the error catching portion
22
.
The physical address of any failing memory cell is replaced by a row redundant line or column redundant line, according to the information stored in the error catching portion
22
.
However, since the information for four memory blocks is repeatedly stored, it is not possible to know which one of the memory blocks contains the defective cell.
For example, if data failure information appears in the first address of the error catching portion
22
, it is not possible to know which memory block among the memory blocks
0
,
2
,
8
and
10
includes the defective memory cell. Also, when the memory cells of different physical addresses are tested in the memory blocks
0
,
2
,
8
and
10
, since the different physical addresses overlap one another in the error catching portion
22
, the physical address at which data failure actually occurs cannot be found. Thus, it is difficult to analyze bit failure.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method for testing a semiconductor memory device having a plurality of memory blocks and memory banks, which can find the memory block of a memory bank to which a defective memory cell belongs.
It is another objective of the present invention to provide an apparatus for testing a semiconductor memory device, which can find the memory block of a memory bank to which a defective memory cell belongs.
Accordingly, to achieve the first objective, there is provided a memory testing method of a semiconductor memory device having a plurality of memory banks, each memory bank having a plurality of memory blocks, each memory block having a plurality of memory cell arrays, each memory cell array having a plurality of memory cells, each memory cell allocated to physical addresses composed of row addresses and column addresses, the method comprising the steps of: (1) selecting one of the memory banks and writing data to all the memory cells formed in the selected memory bank which are allocated to first addresses which are physical; (2) sequentially selecting the memory banks one by one and performing the step (1); (3) generating virtual second addresses, for differentiating the memory cells of the first addresses; and (4) sequentially reading out data from the memory cells of the first addresses while changing the bits of the first and second addresses, to the outside of the semiconductor memory device through data pins, and determining a memory cell array to which a defective memory cell belongs, using the first and second addresses and the numbers of the data pins through which the data are output, if the read data is not the same as the data written in the step (1) or (2).
To achieve the second objective, there is provided an apparatus for testing a semiconductor memory device having a plurality of memory banks, each memory bank having a plurality of memory blocks, each memory block having a plurality of memory cell arrays, each memory cell array having a plurality of memory cells, each memory cell allocated to physical addresses composed of row addresses and column addresses, the apparatus comprising: a pattern generator for generating a pattern composed of first addresses which are physical addresses, having row addresses and column addresses, to which the memory cells are allocated, and first data for being written to the memory cells allocated to the first addresses; a virtual address generator for generating second addresses which are virtual addresses, for differentiating the memory cells of the first addresses; a data detector
Jeon Soon-keun
Kang Sang-soo
Moise Emmanuel L.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
LandOfFree
Method and apparatus for testing semiconductor memory device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for testing semiconductor memory device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing semiconductor memory device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2477167