Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-09-05
2006-09-05
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000
Reexamination Certificate
active
07103813
ABSTRACT:
A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.
REFERENCES:
patent: 6725442 (2004-04-01), Cote et al.
patent: 6933747 (2005-08-01), Bauer et al.
patent: 6996758 (2006-02-01), Herron et al.
“A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based rReconfigurable Systems” Das et al. in VLSI Design Proceedings 1999 pub date Jan. 7-10, 1999.
Toutounchi, Shahin et al.; “FPGA Test and Coverage”;Proceedings of the International Test Conference, 2002, pp. 599-607.
Lee Andy
Pang Anthony
Saini Rahul
Tracy Paul
Wright Adam
Altera Corporation
Britt Cynthia
Lamarre Guy
Townsend and Townsend / and Crew LLP
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