Method and apparatus for testing integrated circuits by...

Details Method and apparatus for testing integrated circuits by... Method and apparatus for testing integrated circuits by...

2007-07-18

2009-11-17

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S030000, C714S032000, C714S043000, C714S709000, C714S712000, C714S715000, C714S716000, C714S717000, C714S718000, C714S719000, C714S720000, C714S733000, C714S734000, C714S736000, C714S738000, C714S742000, C375S225000, C370S222000

Reexamination Certificate

active

07620861

ABSTRACT:
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.

REFERENCES:
patent: 4379259 (1983-04-01), Varadi et al.
patent: 4484329 (1984-11-01), Slamka et al.
patent: 4821238 (1989-04-01), Tatematsu
patent: 4965799 (1990-10-01), Green et al.
patent: 5794175 (1998-08-01), Conner
patent: 5919270 (1999-07-01), Arkin
patent: 5959914 (1999-09-01), Gates et al.
patent: 5995424 (1999-11-01), Lawrence et al.
patent: 6014759 (2000-01-01), Manning
patent: 6055653 (2000-04-01), LeBlanc et al.
patent: 6055661 (2000-04-01), Luk
patent: 6058055 (2000-05-01), Brunelle
patent: 6134690 (2000-10-01), Ivaturi et al.
patent: 6178526 (2001-01-01), Nguyen et al.
patent: 6202186 (2001-03-01), Oonk
patent: 6275962 (2001-08-01), Fuller et al.
patent: 6345372 (2002-02-01), Dieckmann et al.
patent: 6389525 (2002-05-01), Reichert et al.
patent: 6425095 (2002-07-01), Yasui
patent: 6452411 (2002-09-01), Miller et al.
patent: 6525523 (2003-02-01), Soma et al.
patent: 6546511 (2003-04-01), Sim et al.
patent: 6574759 (2003-06-01), Woo et al.
patent: 6594595 (2003-07-01), Yamaguchi et al.
patent: 6598004 (2003-07-01), Ishida et al.
patent: 6615379 (2003-09-01), Tripp et al.
patent: 6646936 (2003-11-01), Hamamatsu et al.
patent: 6687629 (2004-02-01), Yamaguchi et al.
patent: 6701474 (2004-03-01), Cooke et al.
patent: 6731125 (2004-05-01), Chang
patent: 6737852 (2004-05-01), Soma et al.
patent: 6754117 (2004-06-01), Jeddeloh
patent: 6775321 (2004-08-01), Soma et al.
patent: 6795496 (2004-09-01), Soma et al.
patent: 6851076 (2005-02-01), Cook et al.
patent: 6880118 (2005-04-01), Chen et al.
patent: 6888366 (2005-05-01), Kim et al.
patent: 6922439 (2005-07-01), Yamaguchi et al.
patent: 7054358 (2006-05-01), Yamaguchi et al.
patent: 7080292 (2006-07-01), Moore et al.
patent: 7085980 (2006-08-01), Martin-de-Nicolas et al.
patent: 7088122 (2006-08-01), Hartmann et al.
patent: 7092902 (2006-08-01), Eldridge et al.
patent: 7119567 (2006-10-01), Ma et al.
patent: 7127018 (2006-10-01), Yamaguchi et al.
patent: 7131046 (2006-10-01), Volkerink et al.
patent: 7142003 (2006-11-01), Kanbayashi et al.
patent: 7203229 (2007-04-01), Ishida et al.
patent: 7272756 (2007-09-01), Brink et al.
patent: 2001/0047500 (2001-11-01), Tsuto
patent: 2002/0181678 (2002-12-01), Lai et al.
patent: 2003/0208711 (2003-11-01), Frame et al.
patent: 2005/0185708 (2005-08-01), Yamaguchi et al.
patent: 2007/0036256 (2007-02-01), Yamaguchi et al.
patent: 2007/0099590 (2007-05-01), Okabe et al.
patent: 2008/0201621 (2008-08-01), Sato
patent: 2009/0115443 (2009-05-01), Lai et al.
Co-pending U.S. Appl. No. 11/933,796, filed Nov. 1, 2007 Lai, et al.

Affiliated with

Also associated with

Rating

Method and apparatus for testing integrated circuits by... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for testing integrated circuits by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing integrated circuits by... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4136978