Method and apparatus for testing dynamic logic using an...

Electronic digital logic circuitry – With test facilitating feature

Reexamination Certificate

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C326S093000, C326S112000

Reexamination Certificate

active

06181155

ABSTRACT:

BACKGROUND
TECHNICAL FIELD OF THE PRESENT INVENTION
The present invention generally relates to dynamic circuits and more specifically, to methods and apparatus that use the reset pulse to test whether such dynamic logic circuits are operating properly.
BACKGROUND OF THE PRESENT INVENTION
High speed electronic devices such as digital data processors rely on stored data signals for control of instruction signals. High speed devices, thus, require high speed access to stored digital signals. For example in both processing and memory circuits the requirement for high speed operation has lead to increasing densities of integration in electronic circuit design, and circuits which, once triggered, can carry out relatively complex functions autonomously. For example register files and other memory structures represent such devices.
Timing constraints are of critical concern in high performance data processing and memory circuits, as cycle times are reduced for higher speed. Signals require a finite amount of time to propagate through any type of electrical or electronic structure, and the proper function of logic circuits require that the intended signals be present at the inputs in order to obtain the correct output.
Signal propagation time is affected by many factors of circuit design, such as conductor resistance and parasitic capacitances. At high densities of circuit integration, the number of circuits to which a connection is made may present severe design constraints in regard to cycle time. For example, at high integration densities, a connection such as a word or bit line of a memory will present significant RC delays and waveform distortions where the total switched capacitance, (C) is dominated by the sum of device capacitances of a large number of load devices, and the total resistance, (R) is dominated lay the resistance of the long word or bit lines of a small cross-section.
To obtain highest operational speed, and shortest cycle time in logic circuits employing, currently available MOS technology, it is common practice to employ socalled “dynamic” logic circuits in preference to static logic circuits. In general, dynamic circuits have the goal of maximizing the speed at which a logical function (e.g. “evaluation”) is achieved by minimizing the number of switching devices in the evaluation path, and by employing NMOS, rather than the slower-switching PMOS, for the majority of devices in the evaluation path. This optimization of speed of the evaluation path, or “forward path”, is achieved at the cost of subsequently having to “reset”, or “pre-charge”, dynamic nodes, in preparation for the next logic cycle, to a state from which they may be switched to the other logic state most rapidly, and then only when necessary in accordance with input signals which are evaluated.
In general, the total time period for which a reset, or pre-charge, operation can occur, is ultimately derived from a global (master) clock which is distributed throughout the entire chip. Overall, the reset time period is a small portion of the global cycle, and is pre-defined to the circuit designers. The circuit designers typically design the dynamic circuits to reset within the allocated reset pulse width period in order to avoid degrading the critical evaluation time (i.e. faster reset times require larger reset devices which degrade actual time to performance).
Various faults in a dynamic circuit can result in a degraded pre-charging. The faulty circuit does, in fact, pre-charge, but only in a slower than expected fashion. To ensure a defect-free chip these faults must be detected. Current fault testing methods use the entire allocated reset period for testing. The current testing is based upon the assumption that any existing faults within the dyanmic circuit which are marginal (i.e. they require most if not all of the entire reset period to precharge) will not further degrade over time. This assumption is incorrect.
It would, therefore be a distinct advantage to have a method and apparatus that would adequately test for slower than expected pre-charging of a dynamic circuit. The present invention provides such a method and apparatus.
SUMMARY OF THE PRESENT INVENTION
The present invention is a method and apparatus for detecting whether dynamic logic circuits are pre-charing properly. Specifically, a narrowed rreset pulse is used to verify pre-charging, is occurring as designed.


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patent: 5617047 (1997-04-01), Henkels et al.
patent: 5748012 (1998-05-01), Beakes et al.
patent: 5828234 (1998-10-01), Sprauge
patent: 6064245 (2000-05-01), Singh et al.
patent: 6075386 (2000-06-01), Naffziger

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