Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-29
2003-05-13
Ton, David (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06564347
ABSTRACT:
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of testing integrated circuits and more specifically, to an on-chip logic analyzer unit (LAU).
2. Discussion of Related Art
Once an integrated circuit, such as a microprocessor, has been designed and fabricated, the integrated circuit is tested to determine whether it functions as intended and to define the environmental parameters (e.g. die temperatures, power supply noise, voltage levels and/or core clock frequencies) within which it functions as intended.
For post-fabrication validation testing, for example, a logic analyzer may be used to perform a particular level of functional testing. In general terms, a logic analyzer is connected to a device to be tested using one or more probes. A processor in the logic analyzer executes instructions in response to commands received via a logic analyzer user interface. The executed instructions cause the logic analyzer to stimulate the device being tested via the one or more probes with one or more test signals, referred to herein as signal vectors.
In response to receiving a signal vector from the logic analyzer, the device under test generates one or more response signal vectors that are sent to the logic analyzer via the probes and may be displayed on a logic analyzer display. Pass/fail functionality of the device under test may be determined by comparing reference signal vectors stored by the logic analyzer with the response signal vectors received from the device under test.
In order to test an integrated circuit effectively, a logic analyzer should be capable of applying and receiving signal vectors at a rate at least equal to the desired operating speed of the integrated circuit being tested. Thus, as the operating clock frequency of each generation of integrated circuits continues to increase, logic analyzers used to test integrated circuits must also become faster.
As logic analyzers (and other similar testers) increase in speed, however, they also increase in cost and design complexity. Additionally, most integrated circuit manufacturers purchase logic analyzers from external vendors who may have difficulty producing products that meet the integrated circuit manufacturers technical requirements in a timely manner. Further, using logic analyzer probes, it may not be possible to access all of the signals that are desirable to test.
To improve testability, many integrated circuits include “design for testability” (DFT) features that provide for embedded testing of certain integrated circuit functions. Some of these features may be compatible with the IEEE standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture produced by the Joint Test Action Group (JTAG), often referred to simply as JTAG. An integrated circuit device designed in accordance with IEEE Std. 1149.1 provides for test instructions and data to be serially transferred into the device and response data to be serially transferred out of the device using four extra pins included specifically for this purpose.
Other examples of DFT features include scan chains for testing circuits including sequential logic, specialized state machines for generating test patterns for specific circuitry and cyclic redundancy check (CRC) bits to verify programmable circuitry.
DFT features may provide for testing of integrated circuits, including circuits internal to a chip, that are difficult to access using external test equipment. While DFT features can facilitate testing of particular integrated circuit functions, the testing capabilities of each feature may be limited in scope. Thus, DFT features often provide a piecemeal approach to integrated circuit testing.
Built-In Self-Test (BIST) capability (another DFT feature) is also included in many integrated circuit devices. BIST is typically implemented as a microcoded program in microcode Read Only Memory (ROM) to exercise the microarchitectural elements of the host integrated circuit to determine whether they logically operate as specified. Because BIST is a firmware tool, it is relatively inflexible. Further, BIST typically only produces a pass/fail indication such that further and more extensive testing (possibly using an external logic analyzer) must be performed to determine a contributing circuit failure, for example.
SUMMARY OF THE INVENTION
A method and apparatus for testing an integrated circuit are described. In accordance with one embodiment, an apparatus comprises a programmable logic analyzer unit (LAU) embedded within an integrated circuit. The programmable LAU tests a function of the integrated circuit.
Other features and advantages of the present invention will be appreciated from the accompanying drawings and from the detailed description that follows below.
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Faatz Cynthia T.
Intel Corporation
Ton David
LandOfFree
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