Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-04
2005-01-04
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S724000, C714S725000
Reexamination Certificate
active
06839874
ABSTRACT:
Method and apparatus for testing a device embedded in a programmable logic device is described. Because an embedded device, such as a microprocessor core, comprises more input and output pins than a programmable logic device, such as a field programmable gate array, in which it is located, providing a test vector wider than the number of external input and output pins of the programmable logic device is problematic. To solve this problem, at least a portion of the programmable logic device is programmed to function as a vector controller, where a test vector may be provided to the vector controller in sections, reassembled by the vector controller and provided to the embedded device after reassembly. Moreover, a test vector result in response to the test vector input is obtained by the vector controller and sectioned for outputting.
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William B. A
Chan H. C.
Chung Phung M.
Xilinx , Inc.
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