Method and apparatus for testing adjustment of a circuit paramet

Details Method and apparatus for testing adjustment of a circuit paramet Method and apparatus for testing adjustment of a circuit paramet

1997-09-11

2000-08-22

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714733, 324416, G01R 3128

Patent

active

061088048

ABSTRACT:
A voltage regulator is disclosed which is coupled with a programmable trimming circuit by a trim test circuit. When disabled, the trim test circuit passes the logic states of the signals produced by the trimming circuit to the voltage regulator. When enabled, the trim test circuit applies signals to the voltage regulator which correspond with asserted logic states of signals producible by the trimming circuit. Thus, the effect of the trimming circuit on the voltage regulator is testable without actual programming of the trimming circuit.

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patent: 5815511 (1998-09-01), Yamamoto
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