Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-08-22
2002-04-02
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000, C324S416000
Reexamination Certificate
active
06367039
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to integrated circuits having adjustable circuit parameters, and more particularly, to methods and apparatus for testing adjustment of these circuit parameters.
BACKGROUND OF THE INVENTION
During manufacture of integrated circuits, a wide variety of operating characteristics and circuit functions are tested. Because integrated circuit fabrication involves a number of process steps, variations in circuit parameters are commonplace. Thus, integrated circuits are commonly designed to include adjustable circuit parameters, in which adjustment of these parameters occurs following completed fabrication. For example, many integrated circuits include a voltage regulator which receives an externally applied supply voltage and produces a regulated supply voltage for use by other circuitry internal to the integrated circuit. The magnitude of this internal supply voltage is typically adjusted following completed fabrication of the integrated circuit to provide a regulated voltage at the appropriate operating level.
FIG. 1
depicts a voltage regulator
10
of the type used in a wide variety of integrated circuits. The voltage regulator
10
includes a voltage reference circuit
12
and a power stage circuit
14
, whose configuration and operation are well known to those skilled in the art. The voltage reference circuit
12
receives an input voltage V
IN
which is a function of the externally applied supply voltage V
CCX
, as described below. The voltage reference circuit
12
then produces a reference voltage output V
REF
which is input to the power stage circuit
14
. The power stage circuit
14
correspondingly produces a regulated supply voltage V
CCR
for powering other circuits internal to the integrated circuit in which the voltage regulator
10
is included.
Diodes D
1
and D
2
are connected in series between the external supply voltage V
CCX
and a node between the power stage circuit
14
and the voltage reference circuit
12
. As will be understood by those skilled in the art, these diodes are used during burn-in testing, essentially clamping the voltage of the node to a fixed level below V
CCX
, once V
CCX
exceeds an expected operating range.
A plurality of transistors T
1
-T
4
is connected in series with a resistor R between the external supply voltage V
CCX
and ground potential. As depicted, each of the transistors T
1
-T
4
is a PMOS transistor with its gate connected to ground potential. Typically, these transistors have the same channel width and different channel lengths, and these transistors function essentially like resistors. Each of the transistors T
1
-T
4
is connected to a corresponding one of shunting elements S
1
-S
4
, which are switching PMOS transistors connected in parallel with the corresponding transistor. In response to a corresponding one of signals FUSE
1
*-FUSE
4
* applied to its gate, each of the shunting elements S
1
-S
4
can selectively electrically bypass the corresponding one of the transistors T
1
-T
4
, thereby selectively varying the resistance provided by the transistors. The input voltage V
IN
applied to the voltage reference circuit
12
is produced at a node between the resistor R and the transistors T
1
-T
4
. Depending on which of the transistors T
1
-T
4
is electrically shunted, if any, the magnitude of the input voltage V
IN
is correspondingly adjusted. This affects the magnitude of the produced reference voltage V
REF
, which in turn affects the regulated internal supply voltage V
CCR
.
A trimming circuit
16
includes a plurality of programmable fuse elements F
1
-F
4
. Each of the fuse elements F
1
-F
4
is connected in series with a corresponding one of a plurality of transistors
18
between the external supply voltage V
CCX
and ground potential. As depicted, each of the transistors
18
is a PMOS transistor with its gate tied to ground potential and acts as a pull-up transistor. The trimming circuit
16
also includes a plurality of inverters
20
, each of which has its input connected to a node between the corresponding fuse element F
1
-F
4
and transistor
18
. The output signal produced by each of the inverters
20
is the corresponding one of the signals FUSE
1
*-FUSE
4
*. When, for example, the fuse element F
1
is programmed (i.e., is blown), the input to the corresponding inverter
20
is held at a high logic state, and the signal FUSE
1
* is then asserted at a low logic state. When the fuse element F
1
is not programmed, the input to the inverter
20
is then held at a logic low state, and the output signal FUSE
1
* is correspondingly deasserted.
During mass production of integrated circuits having a trimmable voltage regulator like that depicted in
FIG. 1
, measurements of the various producible V
CCR
magnitudes are recorded. Typically, fuse elements are blown and the resulting effect on regulator output is recorded in what is called a trim table. The trim table is usually created by hand measurement of the change in V
CRC
resulting from each fuse that is blown. For some relatively unstable fabrication processes, the resulting trim table can vary widely from lot to lot, wafer to wafer, and even from die to die. Creation of trim tables is time consuming, and many die may be tested to create an accurate trim table for an entire lot. Also, during creation of trim tables, the value of the regulated supply voltage V
CCR
is necessarily permanently altered on those die being tested. Thus, significant inefficiencies exist in current methods of testing and trimming integrated circuits.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, an integrated circuit is provided which includes a primary circuit, a programmable trimming circuit, and a test circuit. The primary circuit has an adjustable circuit parameter, and the programmable trimming circuit is coupled with the primary circuit to apply a first trimming signal to adjust the primary circuit parameter. A test circuit is also coupled with the primary circuit, and is operable to apply a second trimming signal to the primary circuit to test adjustment of the primary circuit parameter. The programmable trimming circuit may be coupled with the primary circuit by the test circuit, with the test circuit passing the first trimming signal to the primary circuit when the test circuit is disabled. When enabled, the test circuit may then block the first trimming signal and substitute therefor the second trimming signal. The primary circuit may be included within a memory device, which in turn may be included within a computer system.
REFERENCES:
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patent: 4739250 (1988-04-01), Tanizawa
patent: 5361001 (1994-11-01), Stolfa
patent: 5440305 (1995-08-01), Signore et al.
patent: 5450030 (1995-09-01), Shin et al.
patent: 5517455 (1996-05-01), McClure et al.
patent: 5563546 (1996-10-01), Tsukada
patent: 5563549 (1996-10-01), Shieh
patent: 5646948 (1997-07-01), Kobayashi
patent: 5742307 (1998-04-01), Watrobski et al.
patent: 5815511 (1998-09-01), Yamamoto
patent: 5838076 (1998-11-01), Zarrabian et al.
patent: 5917754 (1999-06-01), Pathak et al.
patent: 5965997 (1999-10-01), Alwardi et al.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Ton David
LandOfFree
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