Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-08
2005-11-08
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06964004
ABSTRACT:
A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.
REFERENCES:
patent: 5051996 (1991-09-01), Bergeson et al.
patent: 5387862 (1995-02-01), Parker et al.
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6256506 (2001-07-01), Alexander et al.
patent: 6259924 (2001-07-01), Alexander et al.
patent: 6571373 (2003-05-01), Devins et al.
patent: 6771087 (2004-08-01), Oz et al.
Pramodchandran N. Variyam, et al, “Specification-Driven Test Design for Analog Circuits,” International Symposium on Defect and Fault Tolerance in VLSI Systems, 1999, pp. 335-340.
Pramodchandran N. Variyam and Abhijit Chatterjee, “Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements,” Proceedings, VLSI Test Symposium, pp. 132-137, 1998.
Terry Wilson, “Test Challenges of Next-Generation RF Digital Devices,” EE Evaluation Engineering, vol. 39, No. 11, 2000, pp. 31-37.
Abraham Jacob A.
Chakrabarti Sudip
Chatterjee Abhijit
Cherubal Sasikumar
Goodman Douglas
Ardext Technologies, Inc.
Birdwell & Janke, LLP
Ton David
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