Method and apparatus for testing a memory array

Details Method and apparatus for testing a memory array Method and apparatus for testing a memory array

2008-05-06

2008-05-06

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000, C714S734000, C714S719000, C714S742000, C714S030000, C714S042000, C714S054000, C365S201000

Reexamination Certificate

active

07370249

ABSTRACT:
A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is able to be tested at speeds substantially similar to those under typical operating conditions of the memory array without incurring significant die real estate and power penalties.

REFERENCES:
patent: 5311520 (1994-05-01), Raghavachari
patent: 5640509 (1997-06-01), Balmer et al.
patent: 5828825 (1998-10-01), Eskandari et al.
patent: 6370661 (2002-04-01), Miner
patent: 6421794 (2002-07-01), Chen et al.
patent: 6553525 (2003-04-01), Shephard, III
patent: 6646935 (2003-11-01), Akioka
patent: 6829740 (2004-12-01), Rajski et al.
patent: 6993696 (2006-01-01), Tanizaki et al.
patent: 7171596 (2007-01-01), Boehler
patent: 2002/0194545 (2002-12-01), Abbott
patent: 2003/0120974 (2003-06-01), Adams
patent: 2003/0167431 (2003-09-01), Nicolaidis et al.
patent: 2004/0123200 (2004-06-01), Caty et al.

Affiliated with

Also associated with

Rating

Method and apparatus for testing a memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for testing a memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing a memory array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2804901