Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-08
2003-09-02
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S765010
Reexamination Certificate
active
06615379
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains generally to testing electronic components, and more particularly to a system for testing logic devices with an event generator producing a test pattern.
BACKGROUND OF THE INVENTION
As electronic devices or systems become more complex, testing becomes increasingly difficult due to the large number of potential faults and failure modes. One method of testing such systems is applying a series of test vectors using a pattern or event generator, and comparing the result output by the system under test with an expected result. The expected result may be obtained from a simulation of the system under test, or by use of a “gold” standard unit or system that is determined to be fault free. One problem, however, is that a variance from expected performance by the gold standard system will cause the entire test sequence to fail.
SUMMARY OF THE INVENTION
Thus, it is advantageous if such a variance can be quickly detected so that the error can be remedied quickly, or at least more easily diagnosed. Accordingly, there is a need for method and apparatus for testing that can help detect variance of the gold standard system from expected behavior more quickly.
The present invention provides method and apparatus for testing electronic systems. According to one example embodiment, predetermined test vectors are stored with an associated multiple input signature register (MISR) signature, wherein the MISR signature for a test vector is the expected signature of the output of a gold unit in response to the test vector. The actual MISR signature of the output is compared with the expected MISR signature to detect variances from expected behavior, and interrupt testing so that failure analysis may be done. This and various other embodiments of the invention are described below.
REFERENCES:
patent: 6055661 (2000-04-01), Luk
patent: 6452411 (2002-09-01), Miller et al.
Alexander James W.
Tripp Michael J.
De'cady Albert
Dooley Matthew C.
Schwegman Lundberg Woessner & Kluth P.A.
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