Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-02-16
2008-10-28
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
07444568
ABSTRACT:
A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.
REFERENCES:
patent: 3671940 (1972-06-01), Kronies et al.
patent: 3839705 (1974-10-01), Davis et al.
patent: 4042914 (1977-08-01), Curley et al.
patent: 4679194 (1987-07-01), Peters et al.
patent: 5485467 (1996-01-01), Golnabi
patent: 5541879 (1996-07-01), Suh et al.
patent: 5617021 (1997-04-01), Goetting et al.
patent: 5672966 (1997-09-01), Palczewski et al.
patent: 5841867 (1998-11-01), Jacobson et al.
patent: 5900757 (1999-05-01), Aggarwal et al.
patent: 2007/0168736 (2007-07-01), Ottavi et al.
Lyon, Jose A. et al.; “Testability Features of the 68HC16Z1”, International Test Conference 1991; Oct. 26-30, 1991; pp. 122-129 +2 covers sheets and index; IEEE.
Crouch, Alfred L.; “Scan Testing” (3.1.3) and “Logic Built-In Self-Test” (3.27.3); Design for Test for Digital IC's and Embedded Core Systems; 1999; Title pg, Publication Data pg, 2 pg Contents and pp. 96 & 168; Prentice Hall; New Jersey, USA.
Lyon Jose A.
Morrison Gary R.
Moyer William C.
Reipold Anthony M.
Chiu Joanna G.
Freescale Semiconductor Inc.
Singh Ranjeev
Ton David
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