Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-03-21
2006-03-21
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C711S108000, C713S002000, C365S049130
Reexamination Certificate
active
07017089
ABSTRACT:
According to one embodiment of the present invention, the CAM device includes a CAM array that includes a plurality of rows of CAM cells each coupled to a match line, a priority encoder coupled to the match lines to generate an index, a counter and compare logic coupled to the counter and the priority encoder to compare the index and a counter value from the counter.
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Lamarre Guy
NetLogic Microsystems, Inc
Shemwell Mahamedi LLP
Trimmings John P.
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