Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-08
2003-02-18
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S734000, C365S189040
Reexamination Certificate
active
06523145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to testing integrated circuits. More particularly, the present invention relates to a method and apparatus for digital logic testing using built-in test circuitry.
2. Description of Related Art
In general, integrated circuit arrays are tested by providing a known data input at a known address to the array and comparing the output to an expected output. One well known and widely used prior art system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself. This circuit also is called an array built-in self-test (ABIST) circuit or engine. This type of technology allows for high speed testing without having to force correspondence between the array and input/output connections to the chip itself. Random access memory on a chip, such as the memory provided for processors, are usually tested using an ABIST engine.
Some embedded memory designs have content-addressable-memory-type (CAM-type) structures that are significantly more complex than a simple compare function. This CAM-type compare logic does not lend itself to standard ABIST techniques due to its complexity yet cannot be isolated from array cells providing inputs into the compare logic.
Specifically, a standard ABIST testing technique could be used to test a standard CAM. However, in a complex compare structure in which an array core has combinational logic that is closely coupled with the operation of the cells in the array such that each individual cell in the array provides an input into a unique logic function, the operation of the complex compare logic cannot be isolated from the RAM cells due to the characteristic of having as many inputs as there are bits-cells in the array. As a result, standard testing techniques do not provide a mechanism for testing the complex compare logic.
A straightforward yet very inefficient solution to testing such a structure might embed a scannable latch for every bit cell in the array such that the latch could be loaded with a value to be input into the complex compare logic, and the output from the complex compare logic could then be compared against an expected value given the input value. Clearly, such a solution would quickly obviate its very purpose.
The other alternative is to test the complex compare logic using logic test techniques like deterministic test patterns from an ATPG (Automatic Test Pattern Generation) program, or LBIST (Logic Built in Self Test). However, testing of the complex compare logic with these techniques would require writing and then reading each address in the array multiple times. This results in a significant increase in the number and complexity of the test patterns that are required.
Therefore, it would be advantageous to have an improved method and apparatus for selectively applying test vectors to the circuit inputs while minimizing both the amount of test circuitry that is added, and the difficulty of testing the complex CAM compare logic with standard logic test techniques.
SUMMARY OF THE INVENTION
A method and apparatus for testing a contents-addressable-memory type structure using a simultaneous write-thru mode in an array is provided. The circuit to be tested has combinational logic and an array, and the array has bit cells and a logic cells. Each logic cell is uniquely associated with a bit cell such that an output of a bit cell provides an input to a logic cell, and each set of logic cells for an address of the array provides an output data vector from the array. Each cone of logic in the combinational logic receives an output data vector from an associated address in the array as an input data vector, and each cone of logic in the combinational logic is independent from other cones of logic in the combinational logic. A test vector is input to a write port of the array, and a set of logic cell input values are also input into the array. A test write-thru mode signal simultaneously asserts all write wordline signals of the array associated with the write port in order to write the test vector to all addresses of the array. Test vectors can then be applied simultaneously to all the cones in the combinatorial logic instead of having to apply them to one array address at a time, thereby making it feasible to test this combinatorial logic using standard logic testing techniques. The non-CAM compare type array operations are then tested using ABIST techniques.
REFERENCES:
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4680760 (1987-07-01), Giles et al.
patent: 5619462 (1997-04-01), McClure
patent: 5691950 (1997-11-01), McClure
Ngo Tai Dinh
Shephard, III Philip George
England Anthony V. S.
Tu Christine T.
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