Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-24
2007-04-24
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S710000, C714S025000, C714S718000, C714S734000, C714S736000, C714S745000, C365S201000
Reexamination Certificate
active
10725668
ABSTRACT:
A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.
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Brennan Ciaran J.
Eustis Steven M.
Fragano Michael T.
Ouellette Michael R.
Pai Neelesh G.
De'cady Albert
RatnerPrestia
Trimmings John P.
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