Etching a substrate: processes – Gas phase etching of substrate – With measuring – testing – or inspecting
Reexamination Certificate
1999-03-31
2001-10-02
Gulakowski, Randy (Department: 1746)
Etching a substrate: processes
Gas phase etching of substrate
With measuring, testing, or inspecting
C216S067000, C216S084000, C438S014000, C438S926000
Reexamination Certificate
active
06296778
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor test wafers and, more particularly, to a test wafer that effectively simulates “patterned” standard test wafers and can be produced at a reduced cost.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, the necessary related equipment must often be tested and conditioned prior to being used to manufacture integrated circuits. Such testing and conditioning improve the quality and reliability of the manufactured integrated circuits by providing a preview of how the semiconductor manufacturing equipment operates during various processes. For example, “marathon experiments” are often conducted wherein a vast number of wafers are placed in a plasma chamber and etched in a conventional manner. Analysis of various device parameters and the end product during such marathon experiments provides information that is beneficial during the preparation for actual production of integrated circuits. In particular, data regarding particle emissions may be collected during the course of the marathon experiments to anticipate particle failure during the manufacture of integrated circuits.
To carryout such conditioning exercises and marathon experiments on semiconductor manufacturing equipment such as plasma chambers, standard test wafers are normally used in place of standard production wafers. A cross-section of a standard production wafer
10
and a standard test wafer
20
are shown in
FIGS. 1 and 2
, respectively. As shown, the standard test wafer
20
includes a wafer
22
including any type of materials thereon such as aluminum and the like. This standard test wafer
20
further has a layer of photoresist
24
thereon. By this structure, the standard test wafer
20
simulates a pair of uppermost layers
26
of the standard production wafer
10
.
In order to properly simulate a standard production wafer
10
, it is preferred that the photoresist
24
of the standard test wafer
20
be “patterned.” In other words, the resist is ideally applied to the standard test wafer
20
to define a plurality of vias, channels, etc. which in turn leave a percentage of the standard test wafer
20
exposed as shown in FIG.
3
.
Therefore, the use of standard test wafers
20
can be expensive, especially when standard test wafers
20
have multiple layers similar to standard production wafers
10
. This cost often fails to justify many conditioning exercises and marathon experiments which, in turn, leads to reduced quality and reliability during the subsequent processing of standard production wafers
10
.
One known prior art alternative to the use of such “patterned” standard test wafers
20
is to alternate between aluminum wafers and blanket photoresist wafers in a plasma chamber. Such method, however, tends to be cumbersome and time consuming since the aluminum and blanket photoresist wafers must be alternated during use. Further, the aluminum wafers and blanket photoresist wafers are not processed at the same time. As such, the present method fails to effectively simulate the composition of materials being deposited in the plasma chamber during the processing of standard production wafers. This in turn gives rise to detrimental ramifications in particle performance.
There is thus a need for a test wafer that effectively simulates “patterned” standard test wafers and can be produced at a reduced cost.
DISCLOSURE OF THE INVENTION
The present invention includes a method and apparatus for simulating a standard wafer in semiconductor manufacturing equipment. The present invention includes a support layer suitable for being handled by the semiconductor manufacturing equipment. Applied to the support layer is a mixture including a process agent and a material. During use, the present invention simulates a standard wafer including material similar to that in the mixture of the present invention.
By this design, the present invention offers a cost-effective substitution for standard test wafers. Moreover, the present invention better simulates standard test wafers by ensuring that byproducts are produced simultaneously. The ratio of byproducts of the present invention may also be tailored to simulate a specific percentages of area that is exposed through the process agent on a standard test wafer. This is accomplished by varying a volumetric ratio between the process agent and material within the mixture.
These and other advantages of the present invention will become apparent upon reading the following detailed description and studying the various figures of the drawings.
REFERENCES:
patent: 5711848 (1998-01-01), Iturralde
patent: 5866437 (1999-02-01), Chen et al.
patent: 6046061 (2000-04-01), Tsao et al.
Goldspring Gregory J.
O'Donnell Robert J.
Ahmed Shamim
Gulakowski Randy
Lam Research Corporation
Martine & Penilla LLP
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