Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-06-23
2000-01-11
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714726, G11C 2900, G01R 3128
Patent
active
060147628
ABSTRACT:
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A third clocked flip-flop has a third flip-flop data input coupled to an inversion of the second flip-flop output, a third flip-flop scan-in input, a clock input coupled to the signal source, a scan enable input latched low, and a third flip-flop output, the third flip-flop inverting the third flip-flop data input at the third flip-flop output. A first AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the second flip-flop output, and a first AND gate output. A second AND gate has a first input coupled to the first AND gate output, a second input coupled to the third flip-flop output, and a second AND gate output coupled to a write enable signal enabling the SRAM.
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Sanghani Amit D.
Sridhar Narayanan
Sun Microsystems Inc.
Tu Trinh L.
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