Method and apparatus for reducing power dissipation in a prechar

Details Method and apparatus for reducing power dissipation in a prechar Method and apparatus for reducing power dissipation in a prechar

1997-05-23

1999-04-20

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Precharge

36518902, 365204, G11C 700

Patent

active

058963359

ABSTRACT:
Method and apparatus for selectively inverting memory bits (41-49) in a memory (14). In one embodiment a master reversion bit (75) is used to indicate if all memory bits (41-49) have been inverted. In an alternate embodiment, row reversion bits (77) are used to indicate whether the bits in a corresponding row have been inverted. In yet another embodiment, the reversion column reversion bit (202) may be used to indicate whether the row revert bits (77) themselves have been inverted. These control bits (75, 77, 202) determine whether the output from each column of memory (14) is inverted (i.e. reverted to its original logic state) in order to provide the correct logical state at the data output of memory (14).

REFERENCES:
patent: 5572477 (1996-11-01), Jung
patent: 5608681 (1997-03-01), Priebe et al.
patent: 5642314 (1997-06-01), Yamauchi
Cozart, et al.,Patent Application Serial No. 08/363,843, Filed Dec. 27, 1994, Will Issue Jun. 2, 1998 as U.S. Patent 5,761,700.

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