Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-10-18
2005-10-18
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S109000, C711S110000, C711S155000, C711S156000
Reexamination Certificate
active
06957309
ABSTRACT:
In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.
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Gupta Jay K.
Paul Somnath
Blakely , Sokoloff, Taylor & Zafman LLP
Cypress Semiconductor Corporation
Nguyen T
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