4. Multiplex communications
  5. Pathfinding or routing
  6. Switching a message which includes an address header

Somnath Paul

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Architecture for implementing virtual multiqueue fifos

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
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Configurable and memory architecture independent memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Configurable fast clock detection logic with programmable...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
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FIFO memory system and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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FIFO read interface protocol

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
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Profile ID: LFUS-PAI-P-2374358

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