Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-11-21
2003-01-07
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000
Reexamination Certificate
active
06505314
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method and an apparatus for processing defect addresses as are used, for example, in the testing of a semiconductor memory.
After fabrication, every semiconductor module is checked by a test device to determine whether or not fabrication was effected correctly and the semiconductor module has a correct mode of operation. To that end, in the case of a semiconductor memory, for example, each memory cell is checked for a correct mode of operation. In the course of such checking, in a matrix memory, the test device proceeds either column by column or row by row, so that all the rows are checked for a column and then the next column is selected, for which, in turn, all the rows are tested, or all the columns are checked for a row and then all the columns are checked for the next row.
If a defective memory cell is identified, then its address is stored in a defect memory. Because, in particular, in a matrix memory, there are a very large number of memory cells present, a relatively large memory array has to be kept available for corresponding storage of the defect addresses. Because the memory array is usually stored on the semiconductor module, part of the storage capacity of the semiconductor module is required for defect storage.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method and apparatus for processing defect addresses that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that reduces the number of defect addresses determined when checking for defects in a semiconductor component.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for processing addresses of defective elements of a memory component, including the steps of checking the memory component for a correct mode of operation with a predetermined test program, comparing an address of an element with predetermined address ranges, assigning the address to an address range, using the address of the address range to which the address was assigned for the element, comparing the address of the defective element with defect addresses of elements already identified as defective if an element of the memory component is identified as defective, storing the address as a new defect address if the address does not correspond to one of the defect addresses, and not storing the new address if the address corresponds to one of the defect addresses.
In accordance with another mode of the invention, the last four steps are repeated.
In accordance with a further mode of the invention, the address is compared with the defect address stored last as a defect address, a predeterminable number k of defect addresses stored last are compared with one another, and if the address corresponds to the defect address stored last and if the address corresponds to the last k stored defect addresses the address is not stored as a defect address.
In accordance with an added mode of the invention, one of a column address and a row address of a memory element is used as the address in a matrix-type semiconductor memory.
With the objects of the invention in view, there is also provided an apparatus for processing addresses of defective elements determined by a test apparatus, including an evaluation unit, a comparison device connected to the evaluation unit and having a memory configuration with memory arrays connected in series, and comparitors for comparing a newly determined address with an address stored in a first of the memory arrays, some of the comparitors respectively provided for two of the memory arrays one connected downstream of another, the some comparitors comparing addresses stored in the two memory arrays, the some comparitors forwarding an evaluation signal to the evaluation unit if the addresses correspond, and a defect memory. The evaluation unit outputs a command for storing the newly determined address in the defect memory and in the first memory array if the newly determined address does not correspond to the address stored in the first memory array.
In accordance with an additional feature of the invention, the comparison device advances an address previously stored in the first memory array into a second of the memory arrays if the newly determined address is written to the first memory array.
In accordance with yet another feature of the invention, a number k of the memory arrays are connected in series and the address previously stored in a (k−1)
th
memory array is advanced into a k
th
memory array if the newly determined address is read into the first memory array.
In accordance with yet a further feature of the invention, the evaluation unit outputs a command for storing the newly determined address in the defect memory if the same addresses are not stored in a number k of successive ones of the memory arrays connected in series.
In accordance with yet an added feature of the invention, there is provided a preprocessing unit connected to the comparison device and to the evaluation unit, the preprocessing unit receiving the addresses upstream of the comparison device, the preprocessing unit comparing the addresses with predetermined address ranges and assigning the addresses to an address range, and the preprocessing unit forwarding to the comparison device the address of the address range to which the address was assigned.
In accordance with a concomitant feature of the invention, there are provided bank comparison devices, row comparison devices, column comparison devices, a bank evaluation circuit, a row evaluation circuit, a column evaluation circuit, and a decision circuit, and the memory configuration has memory rows, a number of k memory rows are connected in series, a respective one of the memory rows has three memory arrays including a bank address array, a row address array, and a column address array, the bank address arrays, the row address arrays, and the column address arrays of respective ones of the memory rows are connected in series, one of the bank comparison devices is respectively connected to two of the bank address arrays, one of the row comparison devices is respectively connected to every two of the row address arrays, one of the column comparison devices is respectively connected to every two of the column address arrays, all 2 to k
th
bank comparison devices are connected to the bank evaluation circuit, all 2 to k
th
row comparison devices are connected to the row evaluation circuit, all 2 to k
th
column comparison devices are connected to the column evaluation circuit, and the bank evaluation circuit, the row evaluation circuit, and the column evaluation circuit are connected to the decision circuit.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and apparatus for processing defect addresses, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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“High Speed Redundancy Processor” (Bosse), 1984 International Test Conference, Paper No. 9.4, pp. 282-286.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Ton David
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