Method and apparatus for performing test pattern autograding

Details Method and apparatus for performing test pattern autograding Method and apparatus for performing test pattern autograding

2005-10-17

2008-08-05

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07409654

ABSTRACT:
A method, computer program product, and data processing system for minimizing the number of test sequences needed to achieve a desired level of coverage of events in testing a semiconductor design is disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the design under test are transmitted to a “backend” computer for processing. A determination is made as to which test sequences trigger events not already triggered by previously-considered test sequences. An autograde data structure is generated which further reduces the number of test sequences. A preferred embodiment of the present invention may be used to reduce the number of test sequences required, but may also be used to provide test engineers a basis for devising manually-created test sequences to test related events.

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