Method and apparatus for performing error checking

Details Method and apparatus for performing error checking Method and apparatus for performing error checking

2001-11-15

2004-11-16

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

06820227

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to computer architectures and, more particularly, to a method and an apparatus for performing error checking enablement in a computer.
2. Description of Related Art
Upon initialization, electronic components, such as processors, generally perform self-tests on power-up, which is commonly referred to as power-on-reset (POR). The POR typically involves setting latches within the processor to known states, such as logical zeros. After coming out of POR, error-checking logic verifies that the condition of certain signals, i.e., latches, is as expected. The error-checking logic reports an error condition if the circuits do not match the expected values.
Many latches, however, are connected in a serial fashion within a pipeline, and may require two or more clock cycles before reaching a known valid state (in other words, invalid states may exist in the latches directly after coming out of POR). In order to verify the operation of these circuits, therefore, additional logic and/or circuitry is required to prevent an error condition from being reported prior to the complete initialization of the circuit. Furthermore, the additional logic and/or circuitry usually creates additional problems, such as debugging problems, and/or requires additional resources, such as a validity bit.
Therefore, there is a need for a method and a system to selectively enable post-POR error checking in order to suppress false errors.
SUMMARY
The present invention provides a method and an apparatus for suppressing false errors of one or more circuits by selectively enabling error checkers. The method and apparatus utilizes a shifter to shift an enable bit at the rate at which the one or more circuits become initialized. Errors are suppressed if the value from the shifter corresponding to the clock cycle the one or more circuits are initialized is not enabled.


REFERENCES:
patent: 4100605 (1978-07-01), Holman
patent: 4167041 (1979-09-01), Curlander et al.
patent: 4371949 (1983-02-01), Chu et al.
patent: 5224127 (1993-06-01), Okanoue
patent: 6536000 (2003-03-01), Jackson et al.
patent: 6694367 (2004-02-01), Miesbauer et al.

Affiliated with

Also associated with

Rating

Method and apparatus for performing error checking does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for performing error checking, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing error checking will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3284309