Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-04-25
2002-09-17
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S691000, C438S692000, C438S759000, C356S632000
Reexamination Certificate
active
06451700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for measuring planarity of a polished layer.
2. Description of the Related Art
Chemical mechanical polishing (CMP) is a widely used means of planarizing silicon dioxide as well as other types of layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, the surface of the wafer is mechanically and chemically polished.
As semiconductor devices are scaled down, the importance of chemical mechanical polishing to the fabrication process increases. In particular, it becomes increasingly important to control and minimize within-wafer topography variations. For example, in one embodiment, to minimize spatial variations in downstream photolithography and etch processes, it is necessary for the oxide thickness of a wafer to be as uniform as possible (i.e., it is desirable for the surface of the wafer to be as planar as possible).
Those skilled in the art will appreciate that a variety of factors may contribute to producing variations across the post-polish surface of a wafer. For example, variations in the surface of the wafer may be attributed to drift of the chemical mechanical polishing device. Typically, a chemical mechanical polishing device is optimized for a particular process, but because of chemical and mechanical changes to the polishing pad during polishing, degradation of process consumables, and other processing factors, the chemical mechanical polishing process may drift from its optimized state.
Typically, the operating recipes for polishing tools are determined during the process characterization stage, because no in-line techniques are readily available for determine planarity of the polished surface. Based on design factors, such as the topology of the underlying features and the thickness of the layer to be polished, polishing targets are generated to help ensure that the polishing time is sufficient to planarize the process layer being polished without overpolishing and damaging the underlying structures.
FIG. 1A
illustrates a cross-section of an exemplary semiconductor device
100
that is subjected to a planarization process. The semiconductor device
100
includes a plurality of transistor gate electrode stacks
110
formed on a substrate
120
. For clarity and ease of illustration, not all features of the transistors (e.g., source/drain regions, isolation structures, etc.) are shown. An inter-layer dielectric (ILD) layer
130
is formed over the transistor gate electrode stacks
110
. Typically, the ILD layer
130
is a layer of silicon dioxide formed using tetraethoxysilane (TEOS) or fluorine doped tetraethoxysilane (F-TEOS). The ILD layer
130
is polished to planarize a surface
135
of the ILD layer
130
, as shown in FIG.
1
B. If the ILD layer
130
is underpolished, the surface
135
will not be completely planar, which may interfere with formation of features in subsequent layers. If the ILD layer
130
is overpolished, the underlying features (e.g., the gate electrode stacks
110
) may be damaged or the insulative capability of the ILD layer
130
may be reduced.
Another exemplary process layer that is commonly subjected to a polishing operation is a layer of silicon dioxide used to fill shallow trench isolation (STI) structures formed in the substrate between active devices (e.g., transistors) in the semiconductor device. The silicon dioxide layer is formed over a silicon nitride stop layer. The silicon dioxide layer is polished to remove portions that are not disposed in the isolation trenches. The silicon nitride layer serves as a buffer layer to protect the silicon substrate during the polishing process. The polishing process is designed to polish away all of the silicon dioxide layer and a portion of the silicon nitride stop layer. Portions of the silicon nitride stop layer remaining after the polishing process are removed by a stripping process. If the device is overpolished, all of the silicon nitride stop layer may be removed and the silicon substrate may be damaged. If the device is underpolished, not all of the silicon dioxide may be removed, which may interfere with the stripping of the silicon nitride stop layer
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for polishing wafers. The method includes providing a wafer having a grating structure and a process layer formed over the grating structure; illuminating at least a portion of the process layer and the grating structure with a light source; measuring light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile; and determining at least one parameter of an operating recipe of a polishing tool based on the reflection profile.
Another aspect of the present invention is seen in a metrology tool adapted to receive a wafer having a grating structure and a process layer formed over the grating structure. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile. The data processing unit is adapted to determine planarity of the process layer based on the generated reflection profile.
REFERENCES:
patent: 5555474 (1996-09-01), Ledger
patent: 6122064 (2000-09-01), Banet et al.
patent: 6142855 (2000-11-01), Nyui et al.
patent: 6276989 (2001-08-01), Campbell et al.
Lensing Kevin R.
Stirton James Broc
Advanced Micro Devices , Inc.
Ghyka Alexander
Williams Morgan & Amerson P.C.
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