Optics: measuring and testing – By alignment in lateral direction – With registration indicia
Reexamination Certificate
2001-12-27
2004-08-10
Font, Frank G. (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
With registration indicia
C356S399000, C356S400000, C438S007000
Reexamination Certificate
active
06774998
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for identifying misregistration in a complimentary phase shift mask process.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Semiconductor devices are manufactured from wafers of a semiconducting material. Layers of materials are added, removed, and/or treated during fabrication to create the electrical circuits that make up the device. The fabrication essentially comprises four basic operations. Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process.
The four operations typically used in the manufacture of semiconductor devices are:
layering, or adding thin layers of various materials to a wafer from which a semiconductor device is produced;
patterning, or removing selected portions of added layers;
doping, or placing specific amounts of dopants in the wafer surface through openings in the added layers; and
heat treatment, or heating and cooling the materials to produce desired effects in the processed wafer.
Proper formation of sub-sections within a semiconductor device is an important factor in ensuring proper performance of the manufactured semiconductor device. Critical dimensions of the sub-sections generally have to be within a predetermined acceptable margin of error for semiconductor devices to be within acceptable manufacturing quality.
Features are formed in semiconductor devices by patterning various layer of material formed on the wafer. This patterning is generally conducted by forming a photoresist layer over a process layer that is to be patterned. The photoresist layer is then exposed through a photomask to create a pattern in the photoresist layer. Exposed or unexposed portions of the photoresist layer are removed (i.e., depending on the type of photoresist material used) leaving underlying portions of the process layer exposed. The exposed process layer is then removed by performing an etching process while using the patterned layer of photoresist as a mask to thereby duplicate a pattern in the photoresist mask in the process layer.
There are various types of photomasks that may be used for patterning the photoresist layer. A binary mask typically includes a transparent substrate (e.g., quartz) on which a pattern is formed using an opaque material (e.g., chromium). The opaque portions prevent exposure of the underlying photoresist layer thereby transferring the pattern formed in the opaque layer to the photoresist layer. Due to limitations imposed by the wavelength of light used to transfer the pattern, resolution at the edges of the patterns of the photomask degrades, thus limiting the application of the binary mask as the geometry of the features to be formed on the wafer decreases.
Another type of photomask capable of forming smaller features than a typical binary mask is a phase shift mask. Phase shift masks typically allow for the formation of much smaller features than their binary counterparts.
FIGS. 1A and 1B
illustrate top and cross section views an exemplary phase-shift mask
10
, respectively. A trench
20
is formed in a transparent substrate
30
. The difference in thicknesses of the substrate layer
20
in and out of the trench causes a phase shift in the light passing through the mask. At the edges of the trench
20
(i.e., phase edges
40
), the light undergoes a 180 degree phase transition. Interference between the opposite phase light waves results in the formation of a null region beneath the phase edge
40
. Hence, an underlying photoresist layer is not exposed where the null regions form.
The phase shift mask
10
creates null regions wherever there is a 180 degree transition. In some instances, these nulls may form in regions where it is not desirable to form a feature in the underlying photoresist layer. For examples, null regions may form beneath the edges
50
. The patterns of unexposed photoresist formed by these undesired null regions are referred to herein as artifacts. A second masking operation is performed after the phase shift masking operation to expose the photoresist layer in these regions where it is not desired to form features. The second masking operation is typically performed using a binary mask which prevents exposure of the photoresist layer where features are desired and allows exposure of the photoresist layer in the other regions, thus “erasing” the artifacts. This two step masking process is commonly referred to as a complimentary phase shift mask (CPSM) process.
The binary mask may also be used to form other features where the dimensional requirements are not as stringent as those for the features formed using the phase shift mask. Typically, a semiconductor device may include an array of densely-packed transistors. The phase shift mask may be used to pattern the gate electrode lines for these features to allow for a greater density. The device may also employ transistors in other regions of the device where a high feature density is not required. The gate electrode lines for these transistors may be formed using the binary mask.
An important aspect of a CPSM patterning process is overlay control. Overlay control involves measuring the misalignment, or misregistration, between the pattern formed by the phase shift mask and the pattern formed by the binary mask. If a misalignment occurs between the two masks, the binary mask may not erase all of the artifacts formed by the phase shift mask patterning process. As technology facilitates smaller critical dimensions for semiconductor devices, the need for the reduction of misalignment errors increases dramatically.
Generally, a set of photolithography steps is performed on a lot of wafers using a semiconductor manufacturing tool commonly referred to as an exposure tool or a stepper. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally conn
Lensing Kevin R.
Stirton James Broc
Wright Marilyn I.
Advanced Micro Devices , Inc.
Font Frank G.
Lauchman Layla
Williams Morgan & Amerson
LandOfFree
Method and apparatus for identifying misregistration in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for identifying misregistration in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for identifying misregistration in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3344458