Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-02
2004-01-06
Decady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C365S201000
Reexamination Certificate
active
06675335
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of network communications, and more particularly, to the testing of an external system memory of a network interface controller.
BACKGROUND OF THE INVENTION
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access controller (MAC) enabling network interface cards at each station to share access to the media.
Conventional local area network architectures use media access controllers operating according to half-duplex or full-duplex Ethernet (ANSI/IEEE standard 802.3) protocol using a described network medium, such as 10 BASE-T. Newer operating systems require that a network station be able to detect the presence of the network. In an Ethernet 10 BASE-T environment, the network is detected by the transmission of a line pulse by the physical layer (PHY) transceiver. The periodic link pulse on the 10 BASE-T media is detected by a PHY receiver, which determines the presence of another network station transmitting on the network medium based on the detection of the periodic link pulses. Hence, a PHY transceiver at station A is able to detect the presence of station B, without the transmission or reception of data packets, by the reception of link pulses on the 10 BASE-T medium from the PHY transmitter at station B.
Architectures have been developed enabling computers to be linked together using conventional twisted pair telephone lines instead of established local area network media such as 10 BASE-T. Such an arrangement, referred herein as a home network environment, provides the advantage that existing telephone wiring in a home may be used to implement a home network environment. However, telephone lines are inherently noisy due to spurious noise caused by electrical devices in the home, for example dimmer switches, transformers of home appliances, etc. In addition, the twisted pair telephone lines suffer turn-on transients due to on-hook and off-hook and noise pulses from the standard POTS telephones, and electrical systems such as heating and air conditioning systems, etc.
It is therefore important for a MAC to be informed of the conditions existing on a network at any time, and this is especially true in home network architectures. The status information is normally stored by the network controller in an external memory. In addition to the status information, the external memory also stores frame data and control information. The external memory, along with the PC board traces and connections, as well as parts of the logic within the network controller, comprise a memory subsystem. Failures in the memory subsystem may result from electrical or mechanical failure of any of the elements of the system and/or errors in the design of the PC board such as excessive loading or trace length.
In many networking and other products, embedded memory built-in self test (MBIST) circuits are used to test internal static random access memories (SRAMs) at speed. The MBIST is normally a simple circuit that reads or writes one memory location during each access. Recently, external RAM is being used to store the large amount of data required in modern networking applications. A number of different types of external memories, which allow burst mode capability, are being employed. These include pipeline burst SRAM, No Bus Latency (NoBL) SRAM and Zero Byte Turnaround (ZBT) SRAM.
To minimize hardware, the same MBIST which is used to test an internal SRAM may also be used to test the external SRAM. However, a problem arises when testing different types of SRAM. This is due to the fact that whenever a test failure is reported, the scan out address location will not always be the same. The reason for this is that the MBIST address counter increments differently when testing different types of SRAM. For example, due to latency required for pipeline burst SRAM when performing a back-to-back read access operation, the MBIST counter will not always increment. This is not the case, however, for ZBT SRAM, which has no such latency constraint. As a result, it is very difficult to ascertain the exact location of the failed memory location for different types of external SRAM.
SUMMARY OF THE INVENTION
There is a need for a network interface controller arrangement that allows a standard MBIST to be performed on external memories of different types coupled to the controller, which allows pinpointing of the exact location of a failed memory location.
These and other needs are met by embodiments of the present invention which provide a network interface controller comprising an external memory interface configured to be coupled to different types of external memories. A memory type register is configured to store the type of an external memory that is coupled to the external memory interface. The controller also comprises memory built-in self test (MBIST) logic configured to perform a built-in self test of an external memory coupled to the external memory interface. The MBIST logic includes adaptive logic configured to interpret results of the built-in self test differently in accordance with the type of external memory stored in the memory type register.
The adaptive logic employed in the present invention accounts for the different types of external memories that may be connected to the external memory interface of the network interface controller. In particular, the same MBIST can be used to test different types of external memories, with the failing address being accurately determined as the latency of the particular external memory coupled to the network interface is taken into consideration.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of testing an external memory coupled to a network interface controller comprising the steps of determining the type of external memory that is coup to the network interface controller, and performing a MBIST of the external memory interface through an external memory interface on the network interface controller. The same MBIST is performed regardless of the type of external memory. The results of the MBIST are interpreted differently according to the determined type of external memory.
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Chiang Sie Boo
Khou Beng Chew
Wong Jacques
Advanced Micro Devices , Inc.
Chaudry Mujtaba
De'cady Albert
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