Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2000-12-29
2004-04-13
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C710S065000, C710S107000, C711S172000
Reexamination Certificate
active
06721918
ABSTRACT:
FIELD OF THE INVENTION
Embodiments of the present invention relate to data busses. In particular, the present invention relates to a method and apparatus for minimizing the effects generated by simultaneous switching of outputs in a bus.
BACKGROUND
A bus is a collection of wires, interfaces, and control elements through which information is transmitted between components in a computer system. A bus may connect to components such as a processor, cache memory, or Random Access Memory (RAM) and may connect to subsystems or devices such as a disk drive, input device, or output device. The component transmitting information over a bus may be referred to as the “transmitting node” and the component receiving information at the output of the bus may be referred to as the “receiving node.”
Data is typically transmitted over a bus in digital format with each wire or signal in the bus transmitting a single bit of information (i.e., binary value). During normal operation, each signal is either transmitting a voltage in a high range, which may represent the value of “one,” or transmitting a voltage in a low range, which may represent the value of “zero.” A signal may be said to be in a “high state” when it is driving a high voltage range and may be said to be in a “low state” when it is driving a low voltage range. A collection of signals in the bus may be referred to as a “databus.” The individual states of the signals in a databus taken together define a set of states which the bus may be in. For example, when a bus is driving the value of FFFF it is one state, and when the bus is driving the value F0FF it is in another state.
During normal operation of the bus, signals are repeatedly switched between states as dictated by the content of the data being transferred. The state of the bus is sampled by a receiving node at time intervals, or cycles, which may be defined by a clock or strobe. Any signal in the bus may be changed from one cycle to the next, and it is not uncommon for the values being driven on each of the signals in the bus to switch states for consecutive cycles. For example, a large number of signals in a bus will change from one state to another from one cycle to the next (i.e., simultaneously) if a large number of the digital values being transmitted over the bus changes from one clock interval to the next. In a high speed bus the signals may be switched between states at a high rate, such as for example 1 million times per second.
A power supply or “rail” (which may be designated VCC) supplies the power to drive a signal from a low state to a high state. To go from a high state to a low state, the capacitance is drained from the signal to a ground. The switching of states of a large number of signals between cycles is known as simultaneous switching and causes a condition known as the simultaneous switching outputs (“SSO”) effect. For example, when a large number of signals change from a high state to a low state during a clock cycle, this may cause the ground to rise in voltage. Because the ground has risen in voltage, it may take longer to drain the charge from the signals and, thus, longer to change the state of the signals. Similarly, when a large number of signals change from a low state to a high state during a clock cycle, this may cause the VCC to be lowered in voltage. In general, a large change in current relative to time (di/dt) produces supply offsets that may affect input buffers and adjacent drivers. A lower power supply voltage or higher ground voltage may slow outputs. A large di/dt can also cause errors on data strobes and may put noise on adjacent signals.
The SSO effect may be difficult to find, understand and correct and is particularly a problem in high speed busses or busses with a large width. The SSO effect can be minimized by distributing multiple grounds for each bus, for example two or three grounds for every bus pair. However, the use of multiple grounds and supply pins substantially increases the cost of the bus and the board area used.
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pate
Self Keith
Urbanski John
Gandhi Dipakkumar
Intel Corporation
Kenyon & Kenyon
Ton David
LandOfFree
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