Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-03-12
2004-04-06
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
Reexamination Certificate
active
06716754
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming patterns for semiconductor constructions, and in particular applications pertains methods of utilizing contact lithography for forming patterns. The invention also encompasses molds configured to pattern masses associated with semiconductor constructions.
BACKGROUND OF THE INVENTION
A prior art semiconductor construction
10
is described with reference to FIG.
1
. Construction
10
comprises a substrate
12
having a plurality of conductive pads
14
,
16
and
18
supported thereover. Pads
14
,
16
and
18
can comprise various conductive materials, including, for example, copper and/or aluminum. Substrate
12
can comprise, for example, a monocrystalline silicon wafer having a plurality of circuit constructions (not shown), such as memory or logic constructions, supported thereon. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Pads
14
,
16
and
18
correspond to electrical interconnects which join the various circuitry (not shown) associated with substrate
12
to electrical components (not shown) external of substrate
12
. Substrate
12
can be considered an integrated circuit component, and pads
14
,
16
and
18
can correspond to, for example, bonding pads or so-called Level III wiring.
Pads
14
,
16
and
18
can be considered to comprise or define electrical nodes. Presently, efforts are underway to redistribute electrical connections from bonding pads to other regions of semiconductor circuitry. The redistribution of the electrical connections can simplify electrical connection of integrated circuitry associated with a semiconductor construction to other circuitry which is external of the semiconductor construction.
FIG. 1
illustrates a plurality of redistribution layers
20
,
22
, and
24
which are electrically connected with bonding pads
14
,
16
and
18
respectively.
A dielectric material
26
separates redistribution layers
20
,
22
and
24
from one another. Dielectric material
26
can comprise, for example, a so-called low-k dielectric material, with the term “low-k” referring to a dielectric material having a dielectric constant below 3.5. An exemplary low-k dielectric material is CYCLOTENE™, which is available from the Dow Chemical Company™. Redistribution layers
20
,
22
and
24
can be referred to as Level IV wiring, and can comprise, for example, copper and/or aluminum.
An insulative material
28
is formed over redistribution layers
20
,
22
and
24
; and openings are formed through insulative material
28
to redistribution layers
20
,
22
, and
24
. Subsequently, conductive materials
30
and
32
are formed within the openings. Conductive materials
30
and
32
can comprise, for example, a copper seed layer and sputter-deposited copper, respectively. After formation of layers
30
and
32
, a pair of under bump metal layers
34
and
36
are provided, and subsequently solder bumps
38
are formed over the under bump layers and in electrical connection with redistribution layers
20
,
22
and
24
through conductive materials
30
and
32
. Under bump layers
34
and
36
can comprise, for example, nickel and gold, respectively; and solder bumps
38
can comprise, for example, tin-based solder. In further processing (not shown) solder bumps
38
can be connected with conductive materials external of construction
10
to electrically interconnect integrated circuitry associated with structure
10
to such external components.
Numerous difficulties are encountered in forming appropriate openings in insulative material
26
for redistribution layers
20
,
22
and
24
; and further problems are encountered in forming openings in insulative material
28
for conductive materials
30
and
32
. It would be desirable to develop methodology which alleviates or eliminates such problems and difficulties.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The mold is then removed from the low-k dielectric material.
In another aspect, the invention encompasses a method of forming a mold. A template is provided which has a complement of a desired mold pattern thereover. The template is approximately the size of a semiconductor wafer and the desired mold pattern is a pattern utilized for contact lithography during semiconductor processing. A sheet having holes extending therethrough is provided. A mold material precursor is provided between the sheet and the template, and is pressed between the sheet and template. The mold material precursor is cured during the pressing to convert the precursor to a mold material having the desired mold pattern. The mold material penetrates through the openings in the sheet and is joined with the sheet to define a mold comprising the mold material and the sheet. The mold is subsequently removed from the template.
In another aspect, the invention encompasses a mold configured to pattern a mass over a semiconductor substrate during contact lithography of the mass. The mold includes a substantially rigid sheet having holes extending therethrough, and a patterned material joined to the sheet. The patterned material extends through the holes in the sheet, and has a pattern therein which is a reverse image of a pattern which is to be formed in the mass during contact lithography.
REFERENCES:
patent: 5597613 (1997-01-01), Galarneau et al.
patent: 5658575 (1997-08-01), Ribier et al.
patent: 5735985 (1998-04-01), Ghosh et al.
patent: 6110401 (2000-08-01), Lee et al.
patent: 6190929 (2001-02-01), Wang et al.
patent: 6225143 (2001-05-01), Rao et al.
patent: 6482742 (2002-11-01), Chou
patent: 6518189 (2003-02-01), Chou
patent: 6521324 (2003-02-01), Debe et al.
“Information about HS II RTV High Strength Moldmaking Silicone Rubber Product Line” Down Corning; 1992.
“Large scale nanolithography using nanoimprint lithography”; Babak Heidari, Ivan Maximov, Eva-Lema Sarwe, and Lars Montelius; J.Vac.Sci. Techol. B17(6), Nov./Dec. 1999; 1999 American Vacuum Society; pp. 2961-2964.
Website: http://www.dow.com/cyclotene/prods/prod1.htm: Cyclotene: Photosensitive Resins; May 14, 2001.
Website: http://www.dow.com/cyclotene/apps/app11.htm: Cyclotene: Bumping/Redistribution/Wafer Level Packaging (WLP); May 14, 2001.
Website: http://www.dow.com/cyclotene/apps/app13.htm: Cyclotene: Multilayer Interconnects; May 14, 2001.
Website: http://www.dow.com/cyclotene/over.htm: Cyclotene: BCB Properties; May 14, 2001.
Website: http://www.dow.com/cyclotene/over/tg.htm:TgvsCure; May 14, 2001.
“New polymer materials for nanoimprinting”; H. Schulz et al.;J. Vac. Sci. Techol. B18(4) Jul./Aug. 2000; pp. 1861-1865.
Hoang Quoc
Micro)n Technology, Inc.
Nelms David
Wells St. John P.S.
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