Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-08-01
2006-08-01
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07085980
ABSTRACT:
The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.
REFERENCES:
patent: 4194113 (1980-03-01), Fulks et al.
patent: 4687988 (1987-08-01), Eichelberger et al.
patent: 4801870 (1989-01-01), Eichelberger et al.
patent: 5391985 (1995-02-01), Henley
patent: 5570011 (1996-10-01), Henley
patent: 6128757 (2000-10-01), Yousuf et al.
patent: 6260166 (2001-07-01), Bhavsar et al.
patent: 6452411 (2002-09-01), Miller et al.
patent: 6499121 (2002-12-01), Roy et al.
patent: 6760873 (2004-07-01), Hao et al.
patent: 405157806 (1993-06-01), None
patent: 406317631 (1994-11-01), None
“Supplying Known Good Die for MCM Applications Using Low Cost Embedded Testing” by Frisch et al. in International Test Conference Proceedings Publication Date: Oct. 21-25, 1995 pp. 328-335 Inspec Accession No. 5254158.
“Directed-Binary Search in Logic BIST Diagnostics” by Kapur et al. Design, Automation and Test in Europe Conference and Exhibition, 2002 Publication Date: Mar. 4-8, 2002 p. 1121 ISSN: 1530-1591 INSPEC Accession No. 7348478.
“Structured Computer Organization” second edition by Andrew Tanenbaum 1984 Prentice-Hall Inc.
“3 value trace based fault simulation of synchronous sequential circuits” Song et al. in IEEE Transactions of Computer Aided Design of Integrated Circuits and Systems vol. 12 issue 9 Sep. 1993.
“Acceleration of Trace based Fault simulation of combinational circuits circuits” Song et al. in IEEE Transactions of Computer Aided Design of Integrated Circuits and Systems vol. 12 issue 9 Sep. 1993.
“Parallel Pattern Fault Simulation based onStem Faults in Combinational Circuits” Song et al. 1990 International Test conference proceedings Sep. 10-14, 1990 pp. 706-711.
Martin-de-Nicolas Pedro
Meissner Charles Leverett
Saunders Michael Timothy
Britt Cynthia
Carr LLP
Gerhardt Diana R.
Lamarre Guy
LandOfFree
Method and apparatus for determining the failing operation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for determining the failing operation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for determining the failing operation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3690815