Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-28
2011-06-28
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C370S503000, C370S537000
Reexamination Certificate
active
07971115
ABSTRACT:
A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion; transferring data from the first portion to a second portion; outputting data at a second rate from the second portion, the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates.
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Patra Madan M.
Sasaki Paul T.
Smith Murray
Ton David
Xilinx , Inc.
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