Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-05-02
2006-05-02
DeCady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S025000, C714S037000, C716S030000
Reexamination Certificate
active
07039845
ABSTRACT:
A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic for determining a subset of transition fault sites on an IC to be tested, second logic that identifies a longest sensitizable path through each transition fault site of the subset of transition fault sites, and third logic that generates a bounded set of test patterns that test the identified longest sensitizable paths through each transition fault site of the subset of transition fault sites. The present invention combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within reasonable amount of time.
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Rearick Jeff
Sharma Manish
DeCady Albert
Trimmings John P.
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