Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1999-04-30
2001-09-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S761000, C438S764000, C438S788000, C257S632000
Reexamination Certificate
active
06287987
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an improved manufacturing semiconductor device, and, in particular, to a method and apparatus for depositing dielectrics on a semiconductor substrate. Still more particularly, the present invention relates to a method and apparatus for depositing and processing low dielectric aerogel films on a semiconductor substrate.
2. Description of the Related Art
Semiconductor devices are widely used in integrated circuits to create microprocessors and other devices for use in products, such as computers, cellular phones, televisions, and automobiles. These integrated circuits typically contain transistors on a single silicon chip to perform various functions and to store data.
Integrated circuits have continued to shrink in size and increase in complexity with each new generation of devices. As a result, integrated circuits increasingly require very close spacing of interconnect lines. Many integrated circuit designs now include multiple levels of metalization to interconnect the various circuits on the device. The closer spacing of these interconnect lines increases capacitance between adjacent lines. As a consequence, as the device geometry shrinks and densities increase capacitance interference or cross talk between adjacent lines becomes an increasing problem (cross talk is the same as capacitive coupling). It is desirable to shrink the size of the integrated circuits. One reason for decreasing the size is this cross talk effects both limits of achievable speed and degrades the noise margin used to ensure proper operation of the device.
One way to diminish the power consumption and cross talk effects in integrated circuits is to decrease the dielectric constant of the insulator or dielectric separating the conductors in the lines. The most common semiconductor dielectric is silicon dioxide, which has a dielectric constant (k) of about 3.9. In contrast, air has a dielectric constant of just over 1.0. As a result, it becomes more desirable to use lower dielectric materials to offset this problem.
Many of the materials used for producing ultra-low-k dielectric insulators for use in integrated circuits require very specific processing constraints, which are not easily achievable. For example, dielectric layers having porous structure have been employed because it has been recognized that porous dielectric layers having a porosity of generally greater than 50% and in many cases greater than 75% may provide a low dielectric constant insulation for decreasing unwanted capacitive coupling in semiconductor devices. Manufacture of these dielectrics, however, have been difficult because of problems associated with shrinkage during drying of dielectrics. Therefore, it would be advantageous to have an improved method and apparatus for depositing a low-k dielectric material on a semiconductor substrate.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for forming a dielectric layer. A silica precursor solution is deposited onto the surface of a substrate. This solution is spread over the surface of the substrate by spinning the substrate. Thereafter, a catalyst is introduced into the substrate by introducing the catalyst through a filter that causes the catalyst to deposit uniformly on the solution and be distributed homogeneously within the silica precursor solution. The solution is aged and dried using a carrier gas in which the carrier gas is used to place a positive pressure on the solvent within the pores.
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Miller Gayle W.
Shelton Gail D.
LSI Logic Corporation
Luk Olivia
Niebling John F.
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