Method and apparatus for debugging semiconductor devices

Details Method and apparatus for debugging semiconductor devices Method and apparatus for debugging semiconductor devices

2005-12-02

2009-06-09

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07546507

ABSTRACT:
A tool for testing an integrated circuit is provided. The tool includes a vector execution engine, a vector image generation engine and a vector display engine. The vector execution engine applies test patterns to the integrated circuit and captures error data being output from the test patterns. The vector image generation engine generates a file of expected output from the application of the test patterns to the integrated circuit. It should be appreciated that the generation of the vector image file occurs offline from the testing by the vector execution engine. The tool also includes a vector display engine allowing identification of vectors including error data. In one embodiment, a timestamp is associated with the vectors of the vector image file and a timestamp is associated with the vectors of the error data. A method for testing an integrated circuit and a graphical user interface are also included.

REFERENCES:
patent: 5720031 (1998-02-01), Lindsay
patent: 7009625 (2006-03-01), Dickinson
patent: 7103800 (2006-09-01), Hasako et al.

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