Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-06-06
2006-06-06
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S727000
Reexamination Certificate
active
07058869
ABSTRACT:
A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core303have no external access, such as the case when they are surrounded by pattern generators302and pattern compactors305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller301and an output-mask network304to allow designers to mask off selected scan cells311from being compacted in a selected pattern compactor305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller301, output-mask network304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.
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Abdel-Hafez Khader S.
Chao Hao-Jan
Hsu Po-Ching
Kao Shih-Chia
Wang Hsin-Po
Dildine R. Stephen
Syntest Technologies, Inc.
Zegeer Jim
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