Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-10
2007-04-10
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C326S016000, C365S154000, C327S202000
Reexamination Certificate
active
11000435
ABSTRACT:
A method and apparatus are provided for implementing AC power dissipation control during scan operations in scannable latch designs. A scannable latch has a functional data output and a scan data output. A switching control is provided with the functional data output. The switching control is driven to prevent switching of the functional data output during at least part of the scan operations. Then the switching control is disabled enabling switching of the functional data output during functional data operations.
REFERENCES:
patent: 5719876 (1998-02-01), Warren
patent: 5838693 (1998-11-01), Morley
patent: 5907562 (1999-05-01), Wrape et al.
patent: 6853212 (2005-02-01), Chandar et al.
Allen David Howard
Hovis William Paul
De'cady Albert
International Business Machines - Corporation
Pennington Joan
Trimmings John P.
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