Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2007-06-19
2007-06-19
Ho, Tu-Tu (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
C438S780000, C257S048000, C257SE23179, C257SE21530
Reexamination Certificate
active
11160154
ABSTRACT:
A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.
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patent: 2004/0145747 (2004-07-01), Jasapara
Daubenspeck Timothy H.
Gambino Jeffrey P.
Muzzy Christopher D.
Sauter Wolfgang
Zimmerman Jeffrey S.
Brown Edward W.
Ho Tu-Tu
International Business Machines - Corporation
Sabo William D.
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