Method and apparatus for choosing tests for simulation and...

Details Method and apparatus for choosing tests for simulation and... Method and apparatus for choosing tests for simulation and...

2008-01-01

2008-01-01

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S739000, C714S025000, C714S032000, C703S014000

Reexamination Certificate

active

11241417

ABSTRACT:
An apparatus for and method of generating test cases for testing simulated logic circuit designs. The test cases are basically generated automatically in a random fashion, manually, or using some combination of automatic and manual techniques. Each test case has a corresponding success indication. These test cases are provided to the simulated logic design for execution. Following execution, each test case is rated pass or fail by comparison of the result with the corresponding success indication and a reason for failure is recorded for each failure. A significantly smaller list of test cases is prepared by eliminating test cases which do not have a unique reason for failure. The smaller list of test cases is then presented for a simulation run which requires substantially less simulator time and substantially less manual analysis of the results.

REFERENCES:
patent: 5546562 (1996-08-01), Patel
patent: 5719881 (1998-02-01), Yonetoku
patent: 5771243 (1998-06-01), Lee et al.
patent: 5996101 (1999-11-01), Masumoto
patent: 7007251 (2006-02-01), Hekmatpour
patent: 7162674 (2007-01-01), Nozuyama
patent: 2004/0059977 (2004-03-01), Liau

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