Method and apparatus for characterizing features formed on a...

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

11128133

ABSTRACT:
A method and apparatus for testing and characterizing features formed on a substrate. In one embodiment, a test structure is provided that includes a test element having a first side and an opposing second side. A first set of one or more structures defining a first region having a first local density are disposed adjacent the first side of the test element. A second set of one or more structures defining a second region having a second local density are disposed adjacent the second side of the test element. A third set of one or more structures defining a third region having a first global density are disposed adjacent the first region. A fourth set of one or more structures defining a fourth region having a second global density are disposed adjacent the second region.

REFERENCES:
patent: 6552812 (2003-04-01), Xu et al.
patent: 6721922 (2004-04-01), Walters et al.
Park, et al., Multi-Level Test Mask Documentation for Low K Dielectric and Copper Damascene CMP Process, Massachusetts Institute of Technology, 1999, pp. 1-78.
Park, et al., Integrated Chip-Scale Prediction of Copper Interconnect Topography, MRS Spring Meeting, Symposium F: Chemical Mechanical Planarization, San Francisco, CA, Apr. 2003.
Lafevre, et al., Direct Measurement of Planarization Length for Copper Chemical Mechanical Polishing (CMP) Processes Using a Large Pattern Test Mask, Materials Research Society (MRS) Spring Meeting, San Francisco, CA, Apr. 2001.
Schellenberg, Lithography: The Integration of TCAD and EDA, Semiconductor International, Wilsonville, Oregon, Feb. 1, 2004.
Park, et al., Chip-Scale Modeling of Electroplated Copper Surface Profiles, Journal of the Electrochemical Society, 151(6), C418-C430 (2004).
Toprac, et al., The Status and Future of APC Software, Yield Dynamics Inc., Austin, Texas.
Gostein, et al., Characterizing and Monitoring Copper CMP Using Nondestructive Optoacoustic Metrology, Micro Magazine.com, pp. 1-13.
Wafer Nanotopography, MEMC, Application Note AE-008, Aug. 2001.
Santarini, Cadence buy mask prep company in DFM push, EE Design, An EE Times Community, May 7, 2003.
http://www.praesagus.com/site/wafers/300/cu/.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for characterizing features formed on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for characterizing features formed on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for characterizing features formed on a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3750360

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.