Method and apparatus for built-in self test of integrated circui

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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Details

714724, G01R 3128

Patent

active

060853468

ABSTRACT:
A BIST function is provided in which both the routing area devoted to the test signals and the area devoted to the circuits required to implement the BIST routines are minimized, while also including the ability to test a plurality of embedded memories at full speed in parallel. Testing the memories at full speed both reduces test time and improves the quality of the testing.

REFERENCES:
patent: 5784323 (1998-07-01), Adams et al.

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