Method and apparatus for automated generation of expected...

Details Method and apparatus for automated generation of expected... Method and apparatus for automated generation of expected...

2008-01-01

2008-01-01

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

07315972

ABSTRACT:
Method and apparatus for generating expected value data for testing a circuit configured in a programmable logic device (PLD). A simulation model is generated from a circuit representation for the circuit. Nodes in the simulation model configured for readback capture are automatically identified. The circuit representation is simulated as defined by the simulation model. Expected value data is recorded during the simulation in response to the identified nodes. A method and apparatus for testing a circuit configured in a PLD is also described. Expected value data for components of a circuit representation for the circuit is automatically generated using a modeling system, where the components are configured for readback capture. A test stimulus is applied to the circuit and state data is captured. The captured state data is compared with the expected value data.

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Xilinx, Inc.; XAPP139, “Configuration and Readback of Virtex FPGAs Using (JTAG) Boundary Scan”; (v1.6; Sep. 12, 2003; available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124; pp. 1-17.

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