Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-10-18
2008-03-25
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S724000, C714S726000, C714S727000, C714S729000, C714S738000, C703S013000, C703S015000, C716S030000, C716S030000
Reexamination Certificate
active
07350124
ABSTRACT:
The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.
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Hakmi et al., “Implementing a Scheme for External Deterministic Self-Test”, May 5, 2005, IEEE VLSI Symposium, pp. 101-106.
Gloekler Tilman
Habermann Christian
Kiryu Naoki
Kneisel Joachim
Koesters Johannes
Lammes Francis
Rifai D'Ann N.
Trimmings John P
Walder, Jr. Stephen J.
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