Method and apparatus for a RAM circuit having N-nary output inte

Details Method and apparatus for a RAM circuit having N-nary output inte Method and apparatus for a RAM circuit having N-nary output inte

1998-09-09

2000-04-04

Phan, Trong

Static information storage and retrieval

Systems using particular element

Ternary

365207, 365190, G11C 1156

Patent

active

060469315

ABSTRACT:
A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.

REFERENCES:
patent: 5208489 (1993-05-01), Houston
patent: 5208490 (1993-05-01), Yetter
patent: 5424734 (1995-06-01), Hirahara et al.
patent: 5524088 (1996-06-01), Yoshida
patent: 5640108 (1997-06-01), Miller
patent: 5808932 (1998-09-01), Irrinki et al.
patent: 5867423 (1999-02-01), Kapoor et al.

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