Method and a deep sub-micron field effect transistor structure f

Details Method and a deep sub-micron field effect transistor structure f Method and a deep sub-micron field effect transistor structure f

1997-12-15

1999-11-23

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, 438563, 438595, H01L 21336

Patent

active

059899662

ABSTRACT:
A method and a deep sub-micron FET structure for suppressing short channel effects and reducing gate-to-drain overlay capacitance and for making CMOS devices is achieved. The method for making these improved FETs includes forming a gate oxide and a patterned polysilicon layer for gate electrodes. Silicon nitride (Si.sub.3 N.sub.4) first sidewall spacers are formed on the sidewalls of the gate electrodes. After selectively removing the gate oxide adjacent to the first sidewall spacers, second sidewall spacers are formed from a doped oxide that serve as a solid-phase diffusion source. The source/drain contact areas are implanted adjacent to the second sidewall spacers. The substrate is then annealed to diffuse from the second sidewall spacers the lightly doped source/drains (LDDs). The Si.sub.3 N.sub.4 sidewall spacers serve as a diffusion barrier and the LDDs are formed under the Si.sub.3 N.sub.4 spacers contiguous with the FET channel, resulting in reduced gate-to-drain overlay capacitance and improved immunity to hot electron effects. By including three additional masking steps, both N-channel and P-channel FETs can be formed for making CMOS devices.

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